The present invention relates to a reading circuit for a non-volatile memory.
As is known, in a floating gate non-volatile memory cell storage of a logic state is carried out by programming the threshold voltage of the cell itself through the definition of the quantity of electrical charge stored in the floating gate region.
Reading of a memory cell is carried out using a read circuit known as xe2x80x9csense amplifierxe2x80x9d, which, in addition to recognizing the logic state stored in the memory cell, also provides for the correct biasing of the drain terminal of the memory cell.
FIG. 1 illustrates by way of example a known sense amplifier used to read multi-level flash memory cells.
The sense amplifier, indicated as a whole by 1, is a successive approximation sense amplifier comprising a supply line 2 set to a supply voltage VCC; a ground line 4 set to a ground voltage VGND; an array branch connected via an array bit line 8 to a non-volatile memory cell 10, the content of which is to be read; a reference branch 12 connected via a reference bit line 14 to a digital/analog converter (DAC) 16, which draws at an output a reference current IR; a current/voltage converter stage 18 connected to the array and reference branches 6, 12 for converting the currents flowing in these branches respectively into an array potential VM and a reference potential VR; a differential comparator stage 20 for comparing the array and reference potentials VM and VR, and supplying at an output a logic comparison signal COMP indicative of the result of the comparison; and an n-bit successive approximation register (SAR) 22, wherein n is the number of bits stored in the memory cell 10, having an input connected to the output of the comparator stage 20, and a plurality n of outputs connected to respective inputs of the digital/analogue converter 16, for driving the digital/analogue converter 16 in order to vary the reference current IR drawn by the latter at the output, in the manner described in detail hereinafter.
In the example illustrated, the memory cell 10 to be read is a multi-level cell in which four bits (sixteen levels) are stored, and has a gate terminal receiving a reading signal VREAD, a drain terminal connected to the array bit line 8, and a source terminal connected to the ground line 4.
In the example illustrated, the successive approximation register 22 is consequently a four-bit register, and has four outputs, each of which is associated with a respective bit, and at which it supplies four control signals, indicated as B3, B2, B1 and B0, assuming a logic value correlated to the logic value assumed by the corresponding bit.
The array branch 6 comprises an array biasing stage 24 for biasing the drain terminal of the memory cell 10 to a predetermined potential, typically 1 V. In particular, the array biasing stage 24 has a negatively fedback cascode structure formed of an NMOS transistor 26 and a logic inverter 28; the NMOS transistor 26 has a drain terminal connected to the current/voltage converter stage 18, a source terminal connected to the array bit line 8 and to the input terminal of the logic inverter 28, and a gate terminal connected to the output terminal of the logic inverter 28. With this configuration, the electrical potential of the drain terminal of the memory cell 10 is approximately equivalent to the threshold voltage of the logic inverter 28, at which potential, in other words, the logic inverter 28 switches from one logic level to the other.
The reference branch 12 comprises a reference biasing stage 30 altogether identical to the array biasing stage 24, and having a fed-back cascode structure formed of an NMOS transistor 32 and a logic inverter 34; the NMOS transistor 32 has a drain terminal connected to the current/voltage converter stage 18, a source terminal connected to the reference bit line 14 and to the input terminal of the logic inverter 34, and a gate terminal connected to the output terminal of the logic inverter 34.
The current/voltage converter stage 18 is formed of a current mirror comprising a first diode-connected PMOS transistor 36 arranged on the array branch 6, and a second PMOS transistor 38 arranged on the reference branch 12; in particular, the PMOS transistors 36 and 38 have gate terminals connected to one another and to the drain terminal of the first PMOS transistor 36, source terminals connected to the supply line 2, and drain terminals connected to the drain terminals respectively of the NMOS transistor 26 and the NMOS transistor 32, and defining respectively an array node 40 and a reference node 42, at which the aforementioned array potential VM and reference potential VR, respectively, are present and to which the two input terminals of the comparator stage 20 are connected.
The sense amplifier 1 operates as follows. When a constant reading voltage VREAD, having a value greater than the highest threshold voltage which can be programmed in the memory cell 10, is applied to the gate terminal of the memory cell 10, and provided that the drain terminal of the memory cell 10 is kept at a sufficiently low, constant value of approximately 1 V, the memory cell 10 works in the triode operating area, and draws an array current IM which is inversely proportional to the threshold voltage programmed, i.e., the higher its threshold voltage, the lower the current flowing in it.
The array current IM is mirrored onto the reference node 42 by the PMOS transistors 36 and 38 of the current mirror 18, and in the reference node 42 the reference current IR drawn by the digital/analogue converter 16 is subtracted from this mirrored current.
The array potential VM and the reference potential VR of the array node 40 and the reference node 42, respectively, are thus correlated respectively to the array current IM, and to the difference between the reference current IR and the array current IM mirrored onto the reference branch 12, and these potentials are compared with one another by the comparator stage 20, which supplies at an output the comparison signal COMP, which assumes a first high logic level if VM is greater than VR, and a second, low logic level if VM is smaller than VR.
The comparison signal COMP is then supplied to the successive approximation register 22, which, on the basis of the logic level of this signal, modifies the logic level of the control signals B3-B0, by implementing a dichotomous algorithm, which is known and therefore described only briefly hereinafter.
In particular, the successive approximation register 20 controls the digital/analogue converter 16 such as to vary by steps the reference current IR drawn by the converter, on the basis of the logic level assumed by the comparison signal COMP. In detail, as soon as the gate terminal of the memory cell 10 is supplied with the reading signal VREAD, the successive approximation register 22 is controlled such as to set the control signal B3 to the high logic level (most significant bit set to xe2x80x9c1xe2x80x9d). Consequently, the digital/analogue converter 16 draws a reference current IR having a value equivalent to half the maximum value which it can supply (i.e., a value correlated to the weight of the most significant bit which has been set to xe2x80x9c1xe2x80x9d), and this current begins to flow in the reference branch 12.
If the reference current IR is lower than the array current IM mirrored onto the reference branch 12, the potential VR varies towards values which are greater than the array potential VM, and the logic level which is consequently assumed by the comparison signal COMP controls the successive approximation register 22 such as to set the control signal B2 also to the high logic level (second most significant bit set to xe2x80x9c1xe2x80x9d), whereas if the reference current IR is greater than the array current IM mirrored onto the reference branch 12, the potential VR varies towards values which are lower than the array potential VM, and the logic level which is consequently assumed by the comparison signal COMP controls the successive approximation register 22 such as to set the control signal B3 to the low logic level (most significant bit set to xe2x80x9c0xe2x80x9d), and the control signal B2 to the high logic level (second most significant bit set to xe2x80x9c1xe2x80x9d).
In the first case, the reference current IR drawn by the digital/analogue converter 16 is consequently incremented by a value equivalent to a quarter of the maximum value which can be supplied (i.e., by a value correlated to the weight of the second most significant bit which has been set to xe2x80x9c1xe2x80x9d), and thus in total it assumes a value equivalent to three quarters of the maximum current which can be supplied, whereas in the second case the reference current IR drawn by the digital/analogue converter 16 assumes a value equivalent to one quarter of the maximum value which can be supplied.
The comparison is then carried out once more between the new values assumed by the array and reference potentials VM and VR, and consequently the logic levels of the control signal B3-B0 are modified, and by proceeding in this manner with successive approximations, at each comparison step there is determination of the value of one of the four bits stored in the memory cell 10 (dichotomous algorithm), and therefore the four bits stored in the memory cell 10 are written in four steps into the successive approximation register 20.
The main disadvantage of the known sense amplifiers is their high current consumption, particularly in cases when the memory cell to be read is blank, or has a low threshold voltage. In fact, in these cases, the high reading voltage VREAD supplied to the gate terminal of the memory cell to be read, together with the low threshold voltage of the memory cell, causes the current flowing in the memory cell itself to assume a rather high value, approximately 50 xcexcA, which, when multiplied by the number of sense amplifiers which generally operate simultaneously in order to carry out parallel reading of several memory cells, gives rise to an overall consumption which in some applications can be unacceptable.
In addition, a further disadvantage of the known sense amplifiers is to have a reading time which increases substantially when the array and reference current IR and IM assume similar values; in fact in these operating conditions, the variation of the array potential VM is somewhat slow, and it is therefore necessary to wait for a relatively long time before being able to enable the comparator stage 20, and thus to have available the content of the memory cell.
The considerations described above for successive approximation sense amplifiers dedicated to the reading of multi-level memory cells, also apply equally well to sense amplifiers dedicated to reading of flash memory cells, in which a single bit is stored, and in which the reference current IR is constant and generated by means of a reference memory cell having a known content.
An embodiment of the present invention is to provide a reading circuit having a lower current consumption than that of reading circuits according to the known prior art.
The reading circuit advantageously also has a reading time which is substantially the same in all operating conditions.
The present invention overcomes the limitations of the prior art by providing a reading circuit for a nonvolatile memory. The reading circuit includes a first reference voltage, a multilevel array memory cell coupled to receive the first memory reference voltage, an array branch coupled to the multilevel array memory cell and a reference branch coupled to a current generator. The current generator includes a reference memory cell which is connected to a second reference voltage. A current voltage converter is coupled to both the array and reference branches. According to one aspect of the invention, the current voltage converter includes a reference line set to a reference potential and also includes a first diode-connected transistor having a first terminal connected to the reference line. The current voltage converter also includes a second terminal connected to the reference node, and a control terminal connected to the second terminal of the first transistor. The current voltage converter also includes several additional transistors. Preferably the number of additional second transistors is equal or equivalent to the number of bits stored in the array memory cell. The second transistors each have a control terminal interconnected to the control terminals of the other transistors and to the control terminal of the first transistor. Each of the second transistors also has a first terminal connected to the reference line, and also has second terminals coupled to receive respective control signals at its control terminal; a control signal is supplied by a successive approximation register. The current voltage converter supplies an array potential which is correlated to a current flowing in the array branch. The array potential is supplied at an array node. The current voltage converter also supplies a reference potential correlated to a current flowing in the reference branch. The reference potential is supplied at a reference node. The reading circuit also includes an equalization transistor which includes drain and source terminals respectively connected to the array node and the reference node. The reading circuit also includes a comparator that has a first input coupled to the array node and a second input coupled to the reference node. The successive approximation register has an input coupled to the output of the comparator. The successive approximation register provides a plurality of outputs that supply the control signals.
According to other aspects of the invention, various alternative embodiments are provided that similarly provide a reading circuit with a lower current consumption than that of reading circuits according to the known prior art.